Head-of-line blocking

An EthernetSwitch connects a number N of input ports to a number M of output ports (usually N = M) by some sort of SwitchingFabric. Arriving packets need to be buffered somewhere in the system when there is contention until they can be transmitted on the desired output ports. In a typical design, these buffers are located at the input ports. Head-of-line blocking occurs when these buffers are implemented as FIFOs and packets from different input queues are destined for the same output port

HOL_blocking.png

The process that removes packets from the input queue and feeds them into the switching fabric during a working cycle of the switch (called the arbiter, which must run at N times the input rate) can only select one of these queues. Due to the nature of a FIFO, the packets at the head of the other queues effectively block the packets behind them even if there is enough capacity to switch them onto their (uncongested) output ports. This effect limits the throughput of the switch to 58% of its capacity when the input traffic is randomly distributed.

Head-of-line blocking can be avoided, for example, by placing the buffers at the output ports or using shared memory rather than FIFOs for the input buffers. However, shared memory is expensive and buffering at the output requires the SwitchingFabric to run at M times the output rate. Therefore, cheap devices usually don't have these features.

References

-- AlexGall - 05 Sep 2007

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Topic revision: r2 - 2007-09-05 - AlexGall
 
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